000			00305nam a2200133Ia 4500
008			241124s9999 xx 000 0 und d
100			_aSudhakar Yelamanchili
245		0	_aIntroduction to VHDL from Simulation to Synthesis
245		0	_b0.2
260			_b-
260			_c0
300			_a401
942			_cBK
999			_c6321 _d6321